74F524 Datasheet | Philips Semiconductors

FEATURES - 8-Bit bidirectional register with bus-oriented input-output - Independent serial input-output to register - Register bus parator with ‘equal to’, ‘greater than’ and ‘less than’ outputs PIN CONFIGURATION S0 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 1 2 3 4 5 6 7 8 9 10 20 VCC 19 S1 18 SE 17 C/SI 16 C/SO 15 EQ 14 GT 13 LT 12 M 11 CP - Cascadable in groups of 8-bits - Open collector parator outputs for AND-wired expansion - Two’s plement or magnitude pare DESCRIPTION The 74F524 is an 8-bit bidirectional register with parallel input and output, plus serial input and output progressing from MSB to LSB. All data inputs, serial and parallel, are loaded by the rising edge of the clock. The device functions are controlled by two control lines (S0, S1) to execute shift, load, hold and read out. An 8-bit parator examines the data stored in the registers and on the data bus. Three true-High, open collector outputs representing ‘register equal to bus’, ‘register greater than bus’ and ‘register less than bus’ are provided. These outputs can be disabled to the OFF state by the use of Status Enable (SE). A mode control has also been provided to allow Two’s plement as well as magnitude pare. Linking inputs are provided for expansion to longer words. I/O7 GND SF00970 TYPE 74F524 TYPICAL f MAX 65MHz TYPICAL SUPPLY CURRENT (TOTAL) 110m A ORDERING INFORMATION DESCRIPTION MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F524N N74F524D PKG DWG # 20-pin plastic DIP 20-pin plastic SOL SOT146-1 SOT163-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS I/On S0, S1 C/SI CP SE M I/On C/SO LT EQ Parallel data inputs Mode select inputs Status priority or serial data input Clock pulse input (active rising edge) Status enable input (active Low) pare mode select input 3-state parallel data outputs Status priority or serial data output Register less than bus output Register equal to bus output DESCRIPTION 74F(U.L.) HIGH/LOW 3.5/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 150/40 50/33...