74F564 Datasheet | Fairchild Semiconductor

Description The 74F564 is a high-speed, low power octal flip-flop with a buffered mon Clock (CP) and a buffered mon Output Enable (OE). The information presented to the D inputs is sorted in the flip-flops on the LOW-to-HIGH Clock (CP) transition. This device is functionally identical to the 74F574, but has inverted outputs. Features s Inputs and outputs on opposite sides of package allow easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally identical to 74F574 s 3-STATE outputs for bus-oriented applications Ordering Code: Order Number 74F564SJ 74F564PC Package Number M20D N20A Package Description 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009563 .fairchildsemi. Unit Loading/Fan Out Pin Names D0 - D7 CP OE O0- O7 Data Inputs Clock Pulse Input (Active Rising Edge) 3-STATE Output Enable Input (Active LOW) 3-STATE Outputs Description U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 Input IIH/IIL Output IOH/IOL 20 µA/- 0.6 m A 20 µA/- 0.6 m A 20 µA/- 0.6 m A 150/40 (33.3) - 3 m A/24 m A (20 m A) Functional Description The 74F564 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are mon to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Function Table Inputs OE H H H H L L L L CP H D L H L H L H L...