74F564 Datasheet | Philips Semiconductors

FEATURES - 74F564 is broadside pinout version of 74F534 - Inputs and Outputs on opposite side of package allow easy interface to Microprocessors PIN CONFIGURATION OE 1 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 CP - Useful as an Input or Ouput port for Microprocessors - 3-State Ouputs for Bus interfacing - mon Output Enable - 74F574 is a non-inverting version of 74F564 DESCRIPTION The 74F564 has a broadside pinout configuration to facilitate PC board layout and allows easy interface with microprocessors. It is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE) control gates. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active Low Output Enable (OE) controls all eight 3-State buffers independently of the register operation. When OE is Low, data in the register appears at the outputs. When OE is High, the outputs are in high impedance “off” state, which means they will neither drive nor load the bus. GND 10 SF01052 TYPE 74F564 TYPICAL f MAX 180MHz TYPICAL SUPPLY CURRENT (TOTAL) 50m A ORDERING INFORMATION DESCRIPTION 20-Pin Plastic DIP 20-Pin Plastic SOL MERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F564N N74F564D PKG. DWG # SOT146-1 SOT163-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D0 - D7 OE CP Data inputs Output Enable input (active Low) Clock Pulse input (active rising edge) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 150/40 LOAD VALUE HIGH/LOW 20µA/0.6m A 20µA/0.6m A 20µA/0.6m A 3.0m A/24m A Q0 - Q7 3-State outputs NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6m A in the...