74F675A Datasheet | Fairchild Semiconductor

Description The 74F675A contains a 16-bit serial in/serial out shift register and a 16-bit parallel out storage register. Separate serial input and output pins are provided for expansion to longer words. By means of a separate clock, the contents of the shift register are transferred to the storage register. The contents of the storage register can also be loaded back into the shift register. A HIGH signal on the Chip Select input prevents both shifting and parallel loading. Features s Serial-to-parallel converter s 16-Bit serial I/O shift register s 16-Bit parallel out storage register s Recirculating parallel transfer s Expandable for longer words s Slim 24 lead package s 74F675A version prevents false clocking through CS or R/W inputs Ordering Code: Order Number 74F675ASC 74F675APC 74F675ASPC Package Number M24B N24A N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram © 1999 Fairchild Semiconductor Corporation DS009587 .fairchildsemi. Unit Loading/Fan Out Pin Names SI CS SHCP STCP R/W SO Q0- Q15 Description Serial Data Input Chip Select Input (Active LOW) Shift Clock Pulse Input (Active Falling Edge) Store Clock Pulse Input (Active Rising Edge) Read/Write Input Serial Data Output Parallel Data Outputs U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 50/33.3 Input IIH/IIL Output IOH/IOL 20 µA/- 0.6 m A 20 µA/- 0.6 m A 20 µA/- 0.6 m A 20 µA/- 0.6 m A 20 µA/- 0.6 m A - 1 m A/20 m A - 1 m A/20 m A Functional Description The 16-Bit shift register operates in one of four modes, as determined by the signals applied to the Chip Select (CS), Read/Write (R/W) and Store Clock Pulse (STCP) input. State changes are indicated by the...