MM74HC138 Datasheet | Fairchild Semiconductor

MM74HC138 3-to-8 Line Decoder September 1983 Revised February 1999 MM74HC138 3-to-8 Line Decoder General Description The MM74HC138 decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications. The circuit Features high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds parable to low power Schottky TTL logic. The MM74HC138 has 3 binary select inputs (A, B, and C). If the device is enabled, these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one active HIGH enables (G1, G2A and G2B) are provided to ease the cascading of...