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MM74HC139 - Dual 2-To-4 Line Decoder

General Description

The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications.

Key Features

  • s Typical propagation delays.
  • Select to outputs (4 delays): 18 ns Select to output (5 delays): 28 ns Enable to output: 20 ns s Low power: 40 µW quiescent supply power s Fanout of 10 LS-TTL devices s Input current maximum 1 µA, typical 10 pA Ordering Code: Order Number MM74HC139M MM74HC139SJ MM74HC139MTC MM74HC139N Package Number M16A M16D MTC16 N16E Package.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MM74HC139 Dual 2-To-4 Line Decoder September 1983 Revised February 1999 MM74HC139 Dual 2-To-4 Line Decoder General Description The MM74HC139 decoder utilizes advanced silicon-gate CMOS technology, and is well suited to memory address decoding or data routing applications. It possesses the high noise immunity and low power consumption usually associated with CMOS circuitry, yet has speeds comparable to low power Schottky TTL logic. The MM74HC139 contain two independent one-of-four decoders each with a single active low enable input (G1, or G2). Data on the select inputs (A1, and B1 or A2, and B2) cause one of the four normally high outputs to go LOW. The decoder’s outputs can drive 10 low power Schottky TTL equivalent loads, and are functionally as well as pin equivalent to the 74LS139.