NM25C041 Datasheet | Fairchild Semiconductor

NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI) Synchronous Bus) March 1999 NM25C041 4K-Bit Serial Interface CMOS EEPROM (Serial Peripheral Interface (SPI™) Synchronous Bus) General Description The NM25C041 is a 4096-bit MODE 1 SPI (Serial Peripheral Interface) CMOS EEPROM which is designed for high-reliability non-volatile data storage applications. The SPI interface Features a byte-wide format (all data is transferred in 8-bit words) to interface with the Motorola 68HC11 microprocessor, or equivalent, at a 2.1MHz clock transfer rate. (This interface is considered the fastest serial munication method.) This 4-wire SPI interface allows the end user full EEPROM functionality while keeping pin count and space requirements low for maximum PC board space utilization. The SPI interface requires four I/O pins on each EEPROM device: Chip Select (CS), Clock (SCK), Serial Data In (SI), and Serial Data Out (SO), as well as 2 other control pins: Write Protect (WP) and HOLD (HOLD). The Write Protect pin can be used to disable the Write operation and the HOLD pin is used to interrupt the SI datastream and place the device in a Hold state during microprocessor instruction generation. Please refer to the following diagrams and description for more details. All programming cycles are pletely self-timed and do not require an ERASE, or similar setup, before programming any cells. Programming can be performed in 3 modes, address (byte) write, page (4 addresses/bytes) write or partial page write. Furthermore, the EEPROM is provided with 4 levels of write protection wherein the data, once programmed, cannot be altered. This is controlled by the Status Register and is described in greater detail within this datasheet. In order to prevent spurious programming, the EEPROM has both a Write Enable mand, which is immediately disabled after each programming operation, and a Write Protect (WP) pin, which must be pulled HIGH to program. Features s...