Up to 40 MIPS at 80MHz core frequency DSP and MCU funct
Key Features
1.1.1.
Processing Core
Efficient 16-bit 56800 family controller engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with uni.
Full PDF Text Transcription for 56F807 (Reference)
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56F807 Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F807 Rev. 16 09/2007 freescale.com Document Revision History Version History Re...
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16 09/2007 freescale.com Document Revision History Version History Rev. 16 Description of Change Added revision history. Added this text to footnote 2 in Table 3-8: “However, the high pulse width does not have to be any particular percent of the low pulse width.