MC9S08SL8 Overview
MC9S08EL32 MC9S08EL16 MC9S08SL16 MC9S08SL8 Data Sheet HCS08 Microcontrollers MC9S08EL32 Rev.
MC9S08SL8 Key Features
- 40-MHz HCS08 CPU (central processor unit)
- HC08 instruction set with added BGND instruction
- Support for up to 32 interrupt/reset sources
- 16-channel, 10-bit resolution, 2.5 μs conversion time, automatic pare function, temperature sensor, internal bandgap ref
- Two analog parators with selectable interrupt on rising, falling, or either edge of parator output; pare option to fixed
- Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake-up
- Supports LIN 2.0 and SAE J2602 protocols; up to 120 kbps, full LIN message buffering, automatic bit rate and frame synch
- Full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-f
- Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-by
- One 4-channel (TPM1) and one 2-channel (TPM2); selectable input capture, output pare, or buffered edge- or center-aligne