Overview: Freescale Semiconductor Product Brief MSC7110PB Rev. 2, 12/2005 MSC7110
Low-Cost 16-Bit DSP with DDR Controller
DMA (32 ch) ASM2
128 JTAG Port JTAG AMDMA
64 Boot ROM (8 KB) External Memory Interface External Bus
32 to IPBus OCE SC1400 Core AHB-Lite Crossbar Switch ASTH
64 Multiplexer Trace Buffer (8 KB) DSP Extended Core ASEMI
64 from IPBus Host Interface (HDI16)
32 HDI16 Port TDM Fetch Unit Instruction Cache (16 KB) Extended Core Interface AMIC
128 TDM UART RS-232 GPIO GPIO Watchdog 32 APB Bridge ASAPB The MSC7110 device targets high-bandwidth highly putational DSP applications and is optimized for Enterprise class packet telephony applications, providing a petitive price per channel for voice over packet systems. APB AMEC
64 ASAPB
.. Interrupt Control PLL/Clock Interrupts PLL/Clock 32 ASM1
64 ASSB
32 128 64 64 IP Bridge M1 SRAM (64 KB)
P XA XB System Control
32 to/from OCE Event Port Timers I2C I2C Events to EMI to DMA to Crossbar Note: The arrows show the direction of the transfer. IPBus Figure 1. MSC7110 Block Diagram The MSC7110 device is a highly integrated DSP processor that contains the StarCore™ SC1400 core, 64 KB of SRAM memory, a 16 KB ICache, an 8 KB boot ROM, a 128-channel time-division multiplexing (TDM) interface with hardware support for µ/A-law decoding/encoding, a UART, a 32-channel DMA controller, a 16-bit host interface (HDI16) to support an external host processor, a programmable interrupt controller (PIC), an I2C interface, two 16-bit quad cascadable timers, GPIO signals, and an on-chip emulator (OCE) and event port for enhanced debug capability. The SC1400 core has four ALUs and performs at 1000 DSP million multiply accumulates per second (MMACS) with an internal 266 MHz clock at 1.2 V. © Freescale Semiconductor, Inc., 2004, 2005. All rights reserved.
