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MSC7110 - Low-Cost 16-Bit DSP

General Description

Up to 1000 MMACS using an internal 266 MHz clock at 1.2 V.

A multiply-accumulate operation includes a multiply-add instruction with the associated data move and pointer update.

4 data ALUs.

16 data registers, 40 bits each.

27 address registers, 32 bits each.

Key Features

  • Features Table 1 lists the features of the Freescale MSC7110 device. Table 1. MSC7110 Features Feature.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Freescale Semiconductor Product Brief MSC7110PB Rev. 2, 12/2005 MSC7110 Low-Cost 16-Bit DSP with DDR Controller DMA (32 ch) ASM2 128 JTAG Port JTAG AMDMA 64 Boot ROM (8 KB) External Memory Interface External Bus 32 to IPBus OCE SC1400 Core AHB-Lite Crossbar Switch ASTH 64 Multiplexer Trace Buffer (8 KB) DSP Extended Core ASEMI 64 from IPBus Host Interface (HDI16) 32 HDI16 Port TDM Fetch Unit Instruction Cache (16 KB) Extended Core Interface AMIC 128 TDM UART RS-232 GPIO GPIO Watchdog 32 APB Bridge ASAPB The MSC7110 device targets high-bandwidth highly computational DSP applications and is optimized for Enterprise class packet telephony applications, providing a competitive price per channel for voice over packet systems. APB AMEC 64 ASAPB www.DataSheet4U.