MSC8144 Datasheet | Freescale Semiconductor

Freescale Semiconductor Data Sheet: Product Preview Document Number: MSC8144 Rev. 1, 5/2007 FC-PBGA- 783 29 mm × 29 mm Quad Core Digital Signal Processor - Four Star Core™ SC3400 DSP subsystems, each with an SC3400 DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, and low-power Wait and Stop processing modes. - Chip-level arbitration and system (CLASS) that provides full fabric non-blocking arbitration between the processing elements and other initiators and the M2 memory, DDR SRAM controller, device configuration control and status registers, and other targets. - 128 Kbyte L2 shared instruction cache. - 512 Kbyte M2 memory for critical data and temporary data buffering. - 10 Mbyte 128-b8t wide M3 memory. - 96 Kbyte boot ROM. .. - Three input clocks (shared, global, and differential). - Four PLLs (system, core, global, and serial Rapid IO). - DDR controller with up to a 200 MHz clock (400 MHz data rate), 16/32 bit data bus, supporting up to 1 Gbyte in up to two banks and support for DDR1 and DDR2. - DMA controller with 16 bidirectional channels with up to 1024 buffer descriptors, and programmable priority, buffer, and multiplexing configuration. - Up to eight independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 128 Mbps data rate for all channels, with glueless interface to E1 or T1 framers, and can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97. - QUICC Engine™ technology subsystem with dual RISC processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction RAM, supporting three munication controllers with one ATM and two Gigabit Ethernet interfaces, to offload scheduling tasks from the DSP cores. - The two Ethernet controllers support 10/100/1000 Mbps operations via MII/RMII/SMII/RGMII/SGMII and...