MSC8144E Datasheet | Freescale Semiconductor

Freescale Semiconductor Data Sheet: Document Number: MSC8144E Rev. 14, 5/2010 Quad Core Digital Signal Processor FC-PBGA- 783 29 mm × 29 mm - Four Star Core® SC3400 DSP subsystems, each with an SC3400 DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, and low-power Wait and Stop processing modes. - Chip-level arbitration and system (CLASS) that provides full fabric non-blocking arbitration between the processing elements and other initiators and the M2 memory, DDR SRAM controller, device configuration control and status registers, and other targets. - 128 Kbyte L2 shared instruction cache. - 512 Kbyte M2 memory for critical data and temporary data buffering. - 10 Mbyte 128-bit wide M3 memory. - 96 Kbyte boot ROM. - Three input clocks (shared, global, and differential). - Four PLLs (system, core, global, and serial Rapid IO). - Security Engine (SEC0 optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP using 4 crypto-channels with multi-mand chains, integrated controller for assignment of the six execution units (PKEU, DEU, AESU, AFEU, MDEU, and KEU0) and the random number generator (RNG), and XOR engine to accelerate parity checking for RAID storage applications. - DDR controller with up to a 200 MHz clock (400 MHz data rate), 16/32 bit data bus, supporting up to 1 Gbyte in up to two banks and support for DDR1 and DDR2. - DMA controller with 16 bidirectional channels with up to 1024 buffer descriptors, and programmable priority, buffer, and multiplexing configuration. - Up to eight independent TDM modules with programmable word size (2, 4, 8, or 16-bit), hardware-base A-law/μ-law conversion, up to 128 Mbps data rate for all channels, with glueless interface to E1 or T1 framers, and can interface with H-MVIP/H.110 devices, TSI, and codecs such as AC-97. -...