MB911912
Overview
- 32-bit RISC (FR series) , load/store architecture, 5-stage pipeline
- General-purpose registers : 16 × 32-bit
- 16-bit fixed-length instructions (basic instructions) , 1 instruction per cycle
- Includes memory-to-memory transfer, bit manipulation, and barrel shift instructions : Optimized for embedded applications
- Includes function entry/exit instructions and multiple-register load/store instructions : Instruction set supports high level languages
- Register interlock function : For efficient assembly language coding
- Branch instructions with delay slots : Reduced overhead for branch operations
- Internal multiplier unit is supported at instruction level Signed 32-bit multiplication : 5 cycles Signed 16-bit multiplication : 3 cycles
- Interrupts (PC and PS saving) : 6 cycles, 16 priority levels (Continued) s PACKAGE Plastic, LQFP, 120-pin Plastic, FLGA, 144-pin (FPT-120P-M05) (LGA-144P-M02) DataSheet 4 U .com
