MB93423 Datasheet | Fujitsu Semiconductor Limited

DESCRIPTION This specifications describe the implementation of the MB93423, incorporating a processor core (FR403-So C) designed for embedded applications, which is based on a VLIW (Very Long Instruction Word) architecture (the FR-V architecture) . This processor can issue the integer operation instruction, media instruction, and branch instruction, up to two instructions, in units called the “VLIW instruction” on a cycle-by-cycle basis. Also, the processor incorporates the following resources : SDRAM controller (SDRAMC) , interrupt controller (IRC) , DMA controller (DMAC) , asynchronous transfer module (UART) , timer/counter (TIMER/COUNTER) , general-purpose I/O (GPIO) , video display controller (VDC) , video capture controller (VCC) , scaler, audio interface, serial interface (I2C- ) , USB interface, and memory stick interface. The VLIW instruction and these resources achieve an excellent cost performance in a plex of high-performance general-purpose processing and media processing, such as multifunction printers, digital cameras, and portable information terminals. - : Purchase of Fujitsu I2C ponents conveys a license under the Philips I2C Patent Rights to use, these ponents in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. - PACKAGE 337-ball plastic PFBGA (BGA-337P-M03) - FEATURES CPU Core - 2-way 240 MHz or 266 MHz VLIW Processor Core - Peak Performance 480 MIPS (Integer operation performance) at 240 MHz 1920 MOPS + 240 MIPS (media operation performance) at 240 MHz 532 MIPS (Integer operation performance) at 266 MHz 2128 MOPS + 266 MIPS (media operation performance) at 266 MHz - 64 32-bit registers (32GR + 32FR) Cache - Instruction cache : 8 Kbyte (2way) , line size 32 byte - Data cache : 8 Kbyte (2way) , line size 32 byte - Cache line replace algorithm : LRU - lnstruction cache preload instruction (ICPL) , Data cache preload instruction (DCPL) support - Cache lock support of both instruction...