MB93423 Description
This specifications describe the implementation of the MB93423, incorporating a processor core (FR403-SoC) designed for embedded applications, which is based on a VLIW (Very Long Instruction Word) architecture (the FR-V architecture) . This processor can issue the integer operation instruction, media instruction, and branch instruction, up to two instructions, in units called the “VLIW instruction” on a...
MB93423 Key Features
- 2-way 240 MHz or 266 MHz VLIW Processor Core
- 64 32-bit registers (32GR + 32FR) Cache
- Instruction cache : 8 Kbyte (2way) , line size 32 byte
- Data cache : 8 Kbyte (2way) , line size 32 byte
- Cache line replace algorithm : LRU
- lnstruction cache preload instruction (ICPL) , Data cache preload instruction (DCPL) support
- Cache lock support of both instruction and data for each line
- Non-blocking cache (data cache)
- Store buffer : 64-byte (data cache) SDRAM Interface
- SDRAM in accordance with the PC100 or PC133 standard can be connected
MB93423 Applications
- Purchase of Fujitsu I2C ponents conveys a license under the Philips I2C Patent Rights to use, these ponents in an I2C system provided that the system conforms t