MB93461 Datasheet | Fujitsu Semiconductor Limited

DESCRIPTION MB93461 realizes excellent performance in the field by bining advanced general processing and media processing for Digital AV equipments such as Television, Advanced Projector, IP TV Phone, Portable Media Player, etc. The processor core embedded in MB93461 can bine maximum two instructions out of integer operation instruction, media instruction, and branch instruction and can issue them in units of VLIW (Very Long Instruction Word) instruction per cycle. Moreover, peripheral resource modules including MMU (Memory Management Unit) , SDRAM controller (SDRAMC) , interrupt controller (IRC) , DMA controller (DMAC) , asynchronous transfer module (UART) , TIMER/COUNTER, general-purpose input/output (GPIO) , video display controller (VDC) , video capture controller (VCC) , audio interface, serial interface (I2C- ) , USB interface (Full Speed Host/Function) , Memory Stick interface, and SD-IO interface are embedded in MB93461. - : Purchase of Fujitsu I2C ponents conveys a license under the Philips I2C Patent Rights to use, these ponents in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. - PACKAGES 420-ball plastic BGA 400-ball plastic PFBGA (BGA-420P-M25) (BGA-400P-M04) - FEATURES FR450 CPU Core - 2-way VLIW Processor Core - Core Frequency : 400 MHz/360 MHz - MMU is embedded - Peak Performance (Core Frequency : 400 MHz) 800 MIPS (Integer operation performance) , 3200 MOPS + 400 MIPS (Media operation performance, 4MAC + Integer) - 64 32-bit registers (32GR + 32FR) Cache - Instruction cache 32 KB (2way) , line size 32 Byte - Data cache 32 KB (2way) , line size 32 Byte - Non-blocking cache (Data Cache) - 64-byte store buffer (Data Cache) SDRAM interface - SDRAM pliant with PC133 standard can be connected, Variable 32-bit/16-bit data bus and 4 CS Local bus interface - 32-bit address/32-bit, 16-bit, or 8-bit data - Directly connecting SRAM/ROM, etc. is possible JTAG - Boundary scan function pliant...