MBM29F016A Key Features
- Single 5.0 V read, write, and erase Minimizes system level power requirements
- patible with JEDEC-standard mands Pinout and software patible with single-power supply Flash Superior inadvertent write
- 48-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type)
- Minimum 100,000 write/erase cycles
- High performance 70 ns maximum access time
- Sector erase architecture Uniform sectors of 64 K bytes each Any bination of sectors can be erased. Also supports full c
- Embedded Erase™ Algorithms Automatically pre-programs and erases the chip or any sector
- Embedded Program™ Algorithms Automatically programs and verifies data at specified address
- Data Polling and Toggle Bit feature for detection of program or erase cycle pletion
- Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle pletion
