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DAPDNA-2 Datasheet PDF

Fujitsu DAPDNA-2

The DAPDNA-2's dynamic reconfiguration enables three beneficial usage models. Each channel of DNA Direct I/O is 32-bit wide and operates at the maximum DAPDNA-2 system clock frequency of 166 MHz, reaching 32 Gbps. The DNA Direct I/O can operate synchronously on the system clock, or can be controlled by an external clock at a different frequency.
Part No. DAPDNA-2
Datasheet DAPDNA-2 Download
Manufacturer
Fujitsu
Description Dynamically Reconfigurable Processor
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DAPDNA-2 datasheet page 1 preview
DAPDNA-2 Dynamically Reconfigurable Processor
● DAPDNA Architecture The DAPDNA Dynamically Reconfigurable Processor is configurable during run-time to instantly (in one clock) provide the optimal hardware circuitry for application in demand. The DAPDNA has a dual-core architecture, comprised of a RISC core (the DAP) and a dynamically reconfigurable matrix (the DNA). This platform provides the processing performance of hardware with the flexibility of software. DAP (Digital Application Processor)
● High-performance RISC processor
● Controls the dynamic reconfiguration of the DNA DNA (Distributed Network Architecture)
● Dynamically reconfigurable
● Two-dimensional array of 376 Processing Elements (PEs)
● Allows arbitrary configuration of the degree of parallelism and pipeline depth DAPDNA Processor DNA Direct I/O DAP Debug Interface RISC Core Instruction Cache Data Cache High-speed Bus Switch Peripherals DDR-SDRAM DMA Interface Controller DNA DNA Configuration memory
● Dynamic Reconfigu...
DAPDNA-2 page 2 preview