DAPDNA-2 - Dynamically Reconfigurable Processor

Description

/ Example 168 EXM : ALU with 16x16 -> 32 multiplier EXS : ALU with byte-swap instruction EXC, EXR, EXF : 16kB, 8/16/32-bit data width DLE : programmable (1-13) delay DLV : vertical cross-segment delay DLH, DLX : C16L : 16bit address counter for load C16S, C16E, C32L, C32S, C32E : LDB : load buffer f

IPflex

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Datasheet Details

Part number	DAPDNA-2
Manufacturer	IPflex
File Size	1.99 MB
Description	Dynamically Reconfigurable Processor
Datasheet	DAPDNA-2 Datasheet
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www.DataSheet4U.com DAPDNA-2 A Dynamically Reconfigurable Processor with 376 32-bit Processing Elements Tomoyoshi Sato Vice President & CTO IPFlex Inc. HotChips17 16 Aug 2005 Agenda          Overview Design Goals and Decisions Overall Architecture Processing Element (PE) Architecture Interconnect Architecture Application Construction Performance Advanced Usages Summary HotChips 17 16 Aug 2005 <2 > www.DataSheet4U.com DAPDNA-2      32bit RISC + Reconfigurable Fabric + Peripherals Fujitsu 0.11µm 7Cu+1Al 12 M gates 1156-pin FCBGA, 2.4V I/O, 1.2V Core 166 MHz, 3-7 W www.DataSheet4U.

Published: Sep 25, 2008 |