DAPDNA-2 Datasheet | IPflex

Overview Design Goals and Decisions Overall Architecture Processing Element (PE) Architecture Interconnect Architecture Application Construction Performance Advanced Usages Summary Hot Chips 17 16 Aug 2005 <2 > .. - - - - - 32bit RISC + Reconfigurable Fabric + Peripherals Fujitsu 0.11µm 7Cu+1Al 12 M gates 1156-pin FCBGA, 2.4V I/O, 1.2V Core 166 MHz, 3-7 W .. - Suited for stream processing - 10-50x performance of 3GHz general-purpose CPU Hot Chips 17 16 Aug 2005 <3 > Design Goals and Decisions - High performance Massively parallel processing elements .. - Flexibility Field programmable - Versatility Dynamically reconfigurable with small overhead - Ease of use Fixed-frequency coarse-grained ALUs - Scalability High-bandwidth I/O (interconnect) channels Hot Chips 17 16 Aug 2005 <4 > DAPDNA-2 Architecture - CPU for sequential tasks DAP (Digital Application Processor) 32-bit RISC with 2way 8k+8k I/D caches .. - Reconfigurable fabric for parallel processing DNA (Distributed Network Architecture) - - - - - 376 heterogeneous 32-bit processing elements ALUs, RAMs, delays, counters, I/O buffers 4 configuration banks: switchable in one cycle 28 billion ALU operations / s (166MHz x 168) 9 billion 16x16 multiplications / s (166MHz x 56) 2.66 GB/s memory bandwidth (64-bit DDR166) 4 GB/s I/O bandwidth (32-bit x 166MHz x 6ch) Hot Chips 17 16 Aug 2005 <5 > DAPDNA-2 Block Diagram .. Hot Chips...