IPflex DAPDNA-2
Dynamically Reconfigurable Processor
| Part No. | DAPDNA-2 |
|---|---|
| Datasheet | DAPDNA-2 Download |
| Manufacturer |  IPflex |
| Description | Dynamically Reconfigurable Processor |
| Buy | Stock & Price |
DESCRIPTION
/ Example 168 EXM : ALU with 16x16 -> 32 multiplier EXS : ALU with byte-swap instruction EXC, EXR, EXF : 16kB, 8/16/32-bit data width DLE : programmable (1-13) delay DLV : vertical cross-segment delay DLH, DLX : C16L : 16bit address counter for load C16S, C16E, C32L, C32S, C32E : LDB : load buffer from external memory LDX : load buffer from I/O channel STB, STX : HotChips 17 16 Aug 2005 <9 > RAM delay 32 136 counter I/O buffer 24 16 PE Example : ALU with 16x16 MUL FF ROT/MSK FF ROT/MSK FF MUL● Finely pipelined Guarantees 166-MHz operation FF
● Registered input/output Gives sufficient time to interconnect wires FF ALU LU FF FF
● ALU feedback path Supports accumulation in one-cycle throughput
● Stage bypass path (not shown) Reduces latency when some stages are unused 16 Aug 2005 < 10 > HotChips 17 Segmented Interconnect Segment
● 8x8 PEs in 1 segment
● 1-cycle intra-segment interconnect Nearly freely routable
● Inter-segment routing via delay elements on segment boundaries N...
