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MB86943B - Peripherals

General Description

The MB86943B is a bus bridge that allows high-speed [data] transfers between the host processor (SPARClite

Family) and the PCI-bus.

This bridge chip enables SPARClite (host CPU) access in program mode (direct master operation) to devices on a PCI bus.

Key Features

  • Key hardware features.
  • Functions for SL-bus to PCI slave (possible to work in program mode).
  • Functions for PCI-bus to SL-bus slave (possible to work in program mode).
  • Two-channel DMA functions (between the SL-bus and the PCI-bus).
  • Functions to access the SL-bus’s external areas (ECS0 through ECS2).
  • Interrupt communication functions between the SL-bus and the PCI-bus by use of Door Bell and Mail Box. s.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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FUJITSU SEMICONDUCTOR DATA SHEET w . U 4 t Microprocessor SPARClite e e h CMOS S a t a D Peripherals for SPARClite . w w m o c DS07-05604-1E MB86943B s DESCRIPTION The MB86943B is a bus bridge that allows high-speed [data] transfers between the host processor (SPARClite* Family) and the PCI-bus. This bridge chip enables SPARClite (host CPU) access in program mode (direct master operation) to devices on a PCI bus. Also, the SPARClite host can invoke the built-in DMA function on the bridge chip to allow access to devices on the PCI bus. Access from the PCI side to devices on the SPARClite bus (SL bus) is enabled by using the bridge chip slave operation function. The DMA function can be started up from the SL-bus side.