CDP1802A
Key Features
- Minimum instruction fetch-execute time of 5 IlS or 7.5 IlS at VDD = 5 V; 2.51ls or 3.75 IlS at VDD = 10 V
- Any bination of standard RAM and ROM up to 65,536 bytes
- Operates with slow memOfles, up to 1 IlS access time at fCL = 4 MHz
- 8-bit parallel organization with bidirectional data bus and multiplexed addresS bus
- 16 x 16 matrix of registers for use as multiple program counters, data pointers, or data registers
- On-chip DMA, mterrupt, and flag inputs
- Programmable smgle-bit output port
- 91 easy-to-use instructions The RCA-CDP1802A LSI CMOS 8-blt register-oriented central-processing unit (CP
