GS81302T20GE Datasheet | GSI Technology

GS81302T06/11/20/38E-500/450/400/350 165-Bump BGA mercial Temp Industrial Temp 144Mb Sigma DDRTM-II+ Burst of 2 SRAM 500 MHz- 350 MHz 1.8 V VDD 1.8 V or 1.5 V I/O Features - 2.5 Clock Latency - Simultaneous Read and Write Sigma DDRTM Interface - JEDEC-standard pinout and package - Double Data Rate interface - Byte Write controls sampled at data-in time - Burst of 2 Read and Write - On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs - 1.8 V +100/- 100 m V core power supply - 1.5 V or 1.8 V HSTL Interface - Pipelined read operation - Fully coherent read and write pipelines - ZQ pin for programmable output drive strength - Data Valid Pin (QVLD) Support - IEEE 1149.1 JTAG-pliant Boundary Scan - 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package - Ro HS-pliant 165-bump BGA package available Sigma DDR-II™ Family Overview The GS81302T06/11/20/38E are built in pliance with the Sigma DDR-II+ SRAM pinout standard for mon I/O synchronous SRAMs. They are 150,994,944-bit (144Mb) SRAMs. The GS81302T06/11/20/38E Sigma DDR-II+ SRAMs are just one element in a family of low power, low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes The GS81302T06/11/20/38E Sigma DDR-II+ SRAMs are synchronous devices. They employ two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. Each internal read and write operation in a Sigma DDR-II+ B2 RAM is two times wider than the device I/O bus. An input data bus de-multiplexer is used to accumulate ining data before it is simultaneously written to the memory array. An output data multiplexer is used to capture the data produced from a single memory array read and then route it to the appropriate output drivers as needed. Therefore, the address field of a Sigma DDR-II+ B2 RAM is always one address pin...