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GS81313LQ18GK - 144Mb SigmaQuad-IIIe Burst of 2 ECCRAM

Download the GS81313LQ18GK datasheet PDF. This datasheet also covers the GS81313LQ18GK-800 variant, as both devices belong to the same 144mb sigmaquad-iiie burst of 2 eccram family and are provided as variant models within a single manufacturer datasheet.

Description

Symbol Description SA D[35:0] Q[35:0] QVLD[1:0] CK, CK KD[1:0], KD[1:0] CQ[1:0], CQ[1:0] R W PLL RST ZQ ZT RCS MZT[1:0] Address

Read Address is registered on CK and Write Address is registered on CK.

Registered on KD and KD during Write operations.

Features

  • 4Mb x 36 and 8Mb x 18 organizations available.
  • 800 MHz maximum operating frequency.
  • 1.6 BT/s peak transaction rate (in billions per second).
  • 115 Gb/s peak data bandwidth (in x36 devices).
  • Separate I/O DDR Data Buses.
  • Non-multiplexed DDR Address Bus.
  • Two operations - Read and Write - per clock cycle.
  • Burst of 2 Read and Write operations.
  • 3 cycle Read Latency.
  • On-chip ECC with virtually zero SER.
  • 1.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS81313LQ18GK-800-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS81313LQ18GK
Manufacturer GSI Technology
File Size 185.23 KB
Description 144Mb SigmaQuad-IIIe Burst of 2 ECCRAM
Datasheet download datasheet GS81313LQ18GK Datasheet

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Other Datasheets by GSI Technology

Part Number Description
GS81313LQ36GK 144Mb SigmaQuad-IIIe Burst of 2 ECCRAM
GS81313LD18GK 144Mb SigmaQuad-IIIe Burst of 4 ECCRAM
GS81313LD36GK 144Mb SigmaQuad-IIIe Burst of 4 ECCRAM
GS81313LT18GK 144Mb SigmaDDR-IIIe Burst of 2 ECCRAM
GS81313LT36GK 144Mb SigmaDDR-IIIe Burst of 2 ECCRAM

Full PDF Text Transcription

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GS81313LQ18/36GK-800/714/600 260-Pin BGA Com & Ind Temp HSTL I/O 144Mb SigmaQuad-IIIe™ Burst of 2 ECCRAM™ Up to 800 MHz 1.25V ~ 1.3V VDD 1.2V ~ 1.3V VDDQ Features • 4Mb x 36 and 8Mb x 18 organizations available • 800 MHz maximum operating frequency • 1.6 BT/s peak transaction rate (in billions per second) • 115 Gb/s peak data bandwidth (in x36 devices) • Separate I/O DDR Data Buses • Non-multiplexed DDR Address Bus • Two operations - Read and Write - per clock cycle • Burst of 2 Read and Write operations • 3 cycle Read Latency • On-chip ECC with virtually zero SER • 1.25V ~ 1.3V core voltage • 1.2V ~ 1.3V HSTL I/O interface • Configurable ODT (on-die termination) • ZQ pin for programmable driver impedance • ZT pin for programmable ODT impedance • IEEE 1149.
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