GS820E32A Overview
Applications The GS820E32A is a 2,097,152 bit high performance synchronous SRAM with a 2 bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPU’s, the device now finds application in synchronous SRAM applications ranging from DSP main store to networking chip set support. Core and Interface Voltages The GS820E32A operates on a 3.3V power...
GS820E32A Key Features
- FT pin for user configurable flow through or pipelined operation
- Dual Cycle Deselect (DCD) Operation
- 3.3V +10%/-5% Core power supply
- 2.5V or 3.3V I/O supply
- LBO pin for linear or interleaved burst mode
- Internal input resistors on mode pins allow floating mode pins
- Default to Interleaved Pipelined Mode
- Byte write (BW) and/or global write (GW) operation
- mon data inputs and data outputs
- Clock Control, registered, address, data, and control