GS820E32A Datasheet | GSI Technology

GS820E32AT/Q-150/138/133/117/100/66 TQFP, QFP mercial Temp Industrial Temp Features - FT pin for user configurable flow through or pipelined operation. - Dual Cycle Deselect (DCD) Operation. - 3.3V +10%/-5% Core power supply - 2.5V or 3.3V I/O supply. - LBO pin for linear or interleaved burst mode. - Internal input resistors on mode pins allow floating mode pins. - Default to Interleaved Pipelined Mode. - Byte write (BW) and/or global write (GW) operation. - mon data inputs and data outputs. - Clock Control, registered, address, data, and control. - Internal Self-Timed Write cycle. - Automatic power-down for portable applications. - JEDEC standard 100-lead TQFP or QFP package. -150 Pipeline t Cycle 6.6ns 3-1-1-1 t KQ 3.8ns IDD 270m A Flow t Cycle 10.5ns Through t KQ 9ns 2-1-1-1 IDD 170m A -138 -133 -117 -100 -66 7.25ns 7.5ns 8.5ns 10ns 12.5ns 4ns 4ns 4.5 5ns 6ns 245m A 240m A 210m A 180m A 150m A 15ns 15ns 15ns 15ns 20ns 9.7ns 10ns 11ns 12ns 18ns 120m A 120m A 120m A 120m A 95m A 64K x 32 2M Synchronous Burst SRAM Flow Through / Pipeline Reads 150Mhz - 66Mhz 9ns - 18ns 3.3V VDD 3.3V & 2.5V I/O The function of the Data Output register can be controlled by the user via the FT mode pin/bump (Pin 14 in the TQFP, bump 1F in the FPBGA). Holding the FT mode pin/bump low, places the RAM in Flow through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipelined Mode, activating the rising edge triggered Data Output Register. DCD Pipelined Reads The GS820E32A is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable mands to the same degree as read mands. DCD RAMs hold the deselect mand for one full cycle and then begin turning off their outputs just after the second rising edge of clock. Byte Write and Global Write Byte write operation is performed by using byte write enable (BW) input bined with one or more individual byte write...