Datasheet4U Logo Datasheet4U.com

GS820E32A - 64K x 32 / 2M Synchronous Burst SRAM

General Description

The GS820E32A is a 2,097,152 bit high performance synchronous SRAM with a 2 bit burst address counter.

Key Features

  • FT pin for user configurable flow through or pipelined operation.
  • Dual Cycle Deselect (DCD) Operation.
  • 3.3V +10%/-5% Core power supply.
  • 2.5V or 3.3V I/O supply.
  • LBO pin for linear or interleaved burst mode.
  • Internal input resistors on mode pins allow floating mode pins.
  • Default to Interleaved Pipelined Mode.
  • Byte write (BW) and/or global write (GW) operation.
  • Common data inputs and data outputs.
  • Cl.

📥 Download Datasheet

Datasheet Details

Part number GS820E32A
Manufacturer GSI Technology
File Size 344.70 KB
Description 64K x 32 / 2M Synchronous Burst SRAM
Datasheet download datasheet GS820E32A Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
GS8206 3-channel constant current LED driver Genesis
GS8000 DVI / HDMI Extender Gennum Corporation
GS8041 14.5KHZ CMOS Rail-to-Rail I/O Opamp GAINSIL
GS8042 14.5KHZ CMOS Rail-to-Rail I/O Opamp GAINSIL
GS8043 14.5KHZ CMOS Rail-to-Rail I/O Opamp GAINSIL

Other Datasheets by GSI Technology

Part Number Description
GS820E32T 64K x 32 / 2M Synchronous Burst SRAM
GS82032AT 2Mb Synchronous Burst SRAM
GS8256418GB-200 288Mb DCD Sync Burst SRAM
GS8256418GB-250 288Mb DCD Sync Burst SRAM
GS8256418GB-333 288Mb DCD Sync Burst SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
GS820E32AT/Q-150/138/133/117/100/66 TQFP, QFP Commercial Temp Industrial Temp Features • FT pin for user configurable flow through or pipelined operation. • Dual Cycle Deselect (DCD) Operation. • 3.3V +10%/-5% Core power supply • 2.5V or 3.3V I/O supply. • LBO pin for linear or interleaved burst mode. • Internal input resistors on mode pins allow floating mode pins. • Default to Interleaved Pipelined Mode. • Byte write (BW) and/or global write (GW) operation. • Common data inputs and data outputs. • Clock Control, registered, address, data, and control. • Internal Self-Timed Write cycle. • Automatic power-down for portable applications. • JEDEC standard 100-lead TQFP or QFP package. -150 Pipeline tCycle 6.6ns 3-1-1-1 tKQ 3.8ns IDD 270mA Flow tCycle 10.