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GS8342D07BD - 36Mb SigmaQuad-II+ Burst of 4 SRAM

Download the GS8342D07BD datasheet PDF. This datasheet also covers the GS8342D07BD-450 variant, as both devices belong to the same 36mb sigmaquad-ii+ burst of 4 sram family and are provided as variant models within a single manufacturer datasheet.

General Description

Table Symbol Description Type Comments SA Synchronous Address Inputs Input R Synchronous Read Input Active Low W Synchronous Write Input Active Low BW0 BW3 Synchronous Byte Writes Input Active Low NW0 NW1 Synchronous Nybble Writes Input Active Low (x8 onl

Key Features

  • 2.0 Clock Latency.
  • Simultaneous Read and Write SigmaQuad™ Interface.
  • JEDEC-standard pinout and package.
  • Dual Double Data Rate interface.
  • Byte Write controls sampled at data-in time.
  • Burst of 4 Read and Write.
  • On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs.
  • 1.8 V +100/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • Pipelined read operation.
  • Fully co.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS8342D07BD-450-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS8342D07BD
Manufacturer GSI Technology
File Size 226.19 KB
Description 36Mb SigmaQuad-II+ Burst of 4 SRAM
Datasheet download datasheet GS8342D07BD Datasheet

Full PDF Text Transcription for GS8342D07BD (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for GS8342D07BD. For precise diagrams, and layout, please refer to the original PDF.

GS8342D07/10/19/37BD-450/400/350/333/300 165-Bump BGA Commercial Temp Industrial Temp 36Mb SigmaQuad-II+TM Burst of 4 SRAM 450 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O F...

View more extracted text
-II+TM Burst of 4 SRAM 450 MHz–300 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • Burst of 4 Read and Write • On-Die Termination (ODT) on Data (D), Byte Write (BW), and Clock (K, K) inputs • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ pin for programmable output drive strength • Data Valid Pin (QVLD) Support • IEEE 1149.

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