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GS881E18/32/36C(T/D)-xxxIV
100-Pin TQFP & 165-bump BGA 512K x 18, 256K x 32, 256K x 36
Industrial Temp
9Mb Sync Burst SRAMs
250 MHz–150 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O
Features
Linear Burst Order (LBO) input. The Burst function need not
• FT pin for user-configurable flow through or pipeline operation
• Dual Cycle Deselect (DCD) operation
be used. New addresses can be loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
• IEEE 1149.1 JTAG-compatible Boundary Scan
The function of the Data Output register can be controlled by
• 1.8 V or 2.5 V +10%/–10% core power supply
the user via the FT mode pin (Pin 14). Holding the FT mode
• 1.8 V or 2.
GS881E32CGT-xxxIV Datasheet
