TJ2997 Datasheet | HTC KOREA

FEATURES z z z z z z z z Source and sink current Low output voltage offset No external resistors required Linear topology Suspend to Ram (STR) functionality Low external ponent count Thermal Shutdown Available in SOP8, SOP8-PP Packages SOP8 / SOP8-PP PKG APPLICATION z DDR -II and -III Termination Voltage z SSTL Termination z HSTL Termination ORDERING INFORMATION Device TJ2997GD TJ2997GDP Package SOP8 SOP8-PP DESCRIPSION The TJ2997 linear regulator is designed to meet the JEDEC SSTL specifications for termination of DDRSDRAM. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering up to 1.5A continuous current and transient peaks up to 3A with respect to PVIN operating condition in the application as required for DDRSDRAM termination. The TJ2997 also incorporates a VSENSE pin to provide superior load regulation and a VREF output as a reference for the chipset and DIMMs. An additional feature found on the TJ2997 is an active high enable (EN) pin that provides Suspend To RAM (STR) functionality. When EN is pulled low the VTT output will tri-state providing a high impedance output, but, VREF will remain active. A power savings advantage can be obtained in this mode through lower quiescent current. Absolute Maximum Ratings CHARACTERISTIC Supply Voltage to GND Lead Temperature (Soldering, 10 sec) Storage Temperature Range Operating Junction Temperature Range SYMBOL PVIN AVIN VDDQ TSOL TSTG TJOPR MIN. -0.3 -0.3 -0.3 MAX. 6.0 6.0 6.0 260 UNIT V ℃ ℃ ℃ -65 -40 150 125 Remended Operation Range CHARACTERISTIC AVIN to GND PVIN & EN to GND SYMBOL AVIN PVIN & EN MIN. 2.3 0 MAX. 5.5 AVIN UNIT Ordering Information Package SOP8 SOP8-PP Apr, 2011 - R1.0.1 Order No. TJ2997GD TJ2997GDP Description DDR Termination Regulator DDR Termination Regulator 1/13 Package Marking TJ2997G TJ2997G Supplied As Reel...