GENERAL DESCRIPTION
In addition the SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is switched on to sustain t he memory until after V CC returns valid. The HMN4M8DV uses extremely low standby current CMOS SRAM ’s, coupled with small lithium coin cells to provide non volatility without long write-cycle times and the write-cycle limitations associated with EEPROM. FEATURES
w Access time : 55, 70ns w High-density design : 32Mbit Design w Battery internally isolated until power is applied w Industry-standard 40-pin 4,096K x 8 pinout w Unlimited write cycles w Data retention in the absence of VCC w 5-years minimum data retention in absence of power w Automatic write-protection during power-up/power-down cycles w Data is automatically protected during power loss PIN ASSIGNMENT A21 A20 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26...