HDMP-0482 Overview
The HDMP-0482 is an Octal Cell Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) and data valid detection capability included. This device minimizes part count, cost and jitter accumulation while repeating ining signals. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations.
HDMP-0482 Key Features
- Supports 1.0625 GBd fibre channel operation
- Supports 1.25 GBd Gigabit Ethernet (GE) operation
- Octal cell PBC/CDR in one package
- CDR location determined by choice of cable input/output
- Amplitude valid detection on FM_NODE[7] input
- Data valid detection on FM_NODE[0] input
- Run length violation detection
- ma detection
- Configurable for both singleframe and multi-frame detection
- Equalizers on all inputs