HD74AC273 Datasheet | Hitachi Semiconductor

Octal D Flip-Flop Description The HD74AC273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The mon buffered Clock (CP) and Master Reset (MR ) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flops’s Q output All outputs will be forced Low independently of Clock or Data inputs by a Low voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are mon to all storage elements. Features - - - - - - - Ideal Buffer for MOS Microprocessor or Memory Eight Edge-Triggered D Flip-Flops Buffered mon Clock Buffered, Asynchronous Master Reset See HD74AC373 for Transparent Latch Version See HD74AC374 for 3-State Version Outputs Source/Sink 24 m A Pin Arrangement MR 1 Q0 2 D0 3 D1 4 Q1 5 Q2 6 D2 7 D3 8 Q3 9 Gnd 10 (Top view) 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP Logic Symbol D0 D1 D2 D3 D4 D5 D6 D7 CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Pin Names D0 - D7 MR CP Q0 - Q7 Data Inputs Master Reset Clock Pulse Input Data Outputs Logic Diagram D0 CP D1 D2 D3 D4 D5 D6 D7 D CP RD MR D CP RD D CP RD D CP RD D CP RD D CP RD D CP RD D CP...