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HD74AC273 - Octal D Flip-Flop

General Description

The HD74AC273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs.

The common buffered Clock (CP) and Master Reset (MR ) inputs load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered.

Key Features

  • Ideal Buffer for MOS Microprocessor or Memory Eight Edge-Triggered D Flip-Flops Buffered Common Clock Buffered, Asynchronous Master Reset See HD74AC373 for Transparent Latch Version See HD74AC374 for 3-State Version Outputs Source/Sink 24 mA HD74AC273 Pin Arrangement MR 1 Q0 2 D0 3 D1 4 Q1 5 Q2 6 D2 7 D3 8 Q3 9 Gnd 10 (Top view) 20 VCC 19 Q7 18 D7 17 D6 16 Q6 15 Q5 14 D5 13 D4 12 Q4 11 CP Logic Symbol D0 D1 D2 D3 D4 D5 D6.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HD74AC273 Octal D Flip-Flop Description The HD74AC273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR ) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flops’s Q output All outputs will be forced Low independently of Clock or Data inputs by a Low voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.