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HD74AC273 - Octal D-Type Flip-Flop

General Description

The HD74AC273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs.

The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered.

Key Features

  • Ideal Buffer for MOS Microprocessor or Memory.
  • Eight Edge-Triggered D Flip-Flops.
  • Buffered Common Clock.
  • Buffered, Asynchronous Master Reset.
  • See HD74AC373 for Transparent Latch Version.
  • See HD74AC374 for 3-State.

📥 Download Datasheet

Datasheet Details

Part number HD74AC273
Manufacturer Renesas
File Size 238.51 KB
Description Octal D-Type Flip-Flop
Datasheet download datasheet HD74AC273 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HD74AC273 Octal D-Type Flip-Flop REJ03D0265–0200Z (Previous ADE-205-386 (Z)) Rev.2.00 Jul.16.2004 Description The HD74AC273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flops’s Q output All outputs will be forced Low independently of Clock or Data inputs by a Low voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.