HD74AC273 Overview
The HD74AC273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The mon buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flops’s Q output All outputs will be forced Low independently of Clock or Data inputs by a Low voltage level on the MR input. The device is useful for
HD74AC273 Key Features
- Ideal Buffer for MOS Microprocessor or Memory
- Eight Edge-Triggered D Flip-Flops
- Buffered mon Clock
- Buffered, Asynchronous Master Reset
- See HD74AC373 for Transparent Latch Version
- See HD74AC374 for 3-State
HD74AC273 Applications
- Ideal Buffer for MOS Microprocessor or Memory
