HD74HC155 Datasheet | Hitachi Semiconductor

Dual 2-to-4-line Decoders/Demultiplexers Description This circuit Features dual 1-line-to-4-line demultiplexer with individual strobes and mon binary-address input. When both sections are enabled by the strobes, the mon binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8line demultiplexer without external gating. Features - - - - - High Speed Operation: tpd (A or B to Y) = 15 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table 2-line-to-4-line Decoder/1-line-to-4-line Demultiplexer Inputs Select B X L L H H X A X L H L H X Strobe 1G H L L L L X Data 1C X H H H H L Outputs 1Y0 H L H H H H 1Y1 H H L H H H 1Y2 H H H L H H 1Y3 H H H H L H Inputs Select B X L L H H X A X L H L H X Strobe 2G H L L L L X Data 2C X L L L L H Outputs 2Y0 H L H H H H 2Y1 H H L H H H 2Y2 H H H L H H 2Y3 H H H H L H 3-line-to-8-line Decoder/1-line-to-8-line Demultiplexer Inputs Select C X L L L L H H H H B X L L H H L L H H A X L H L H L H L H Strobe Data G H L L L L L L L L Outputs 0 2Y0 H L H H H H H H H 1 2Y1 H H L H H H H H H 2 2Y2 H H H L H H H H H 3 2Y3 H H H H L H H H H 4 1Y0 H H H H H L H H H 5 1Y1 H H H H H H L H H 6 1Y2 H H H H H H H L H 7 1Y3 H H H H H H H H L Notes: 1. C: inputs 1C and 2C connected together 2. G: inputs 1G and 2G connected together 3. X: irrelevant Pin Arrangement Data 1 1C Strobe 1G 2 Select Input B 3 1Y3 4 1Y2 5 Outputs 1Y1 6 1Y0 7 GND 8 (Top view) 1Y1 1Y0 1Y3 1Y2 B B A A B B A A 2Y1 2Y0 1C 1G 16 VCC 15 Data 2C Strobe 14 2G Select 13 Input A 2C 2G 2Y3...