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HD74HC4017 - Decade Counter/Divider

General Description

The HD74HC4017 is a 5-stage divide-by-10 Johnson counter with ten decoded outputs and a carry-out bit.

High-speed operation and spike-free outputs are obtained by use of the Johnson decade counter configuration.

Key Features

  • High Speed Operation High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HC4017 Function Table C L X X CE X H X L X X H Notes: 1. X: Don’t care 2. If n < 5 Carry = “H”, Otherwise = “L” R L L H L L L L Decode Output = n n n Q0 n+1 n n n+1 Pin Arrangement Q5 Q1 Q0 Q2 Q6 Q7 Q3 GND 1 2 3 4 5 6 7 8 (Top view) Q1 Q0 Q2.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74HC4017 Decade Counter / Divider Renesas
HD74HC4020 14-stage Binary Counter Renesas
HD74HC4022 Octal Counters/Dividers Renesas
HD74HC4024 7-stage Binary Counter Renesas
HD74HC4040 12-stage Binary Counter Renesas

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HC4020 14-stage Binary Counter
HD74HC4022 Octal Counters/Dividers
HD74HC4024 7-stage Binary Counter
HD74HC4040 12-stage Binary Counter
HD74HC4051 8-Channel Analog Multiplexer/Demultiplexer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HD74HC4017 Decade Counter/Divider Description The HD74HC4017 is a 5-stage divide-by-10 Johnson counter with ten decoded outputs and a carry-out bit. High-speed operation and spike-free outputs are obtained by use of the Johnson decade counter configuration. The ten decoded outputs are normally low and go high only at their respective decimal time periods. A high signal on Reset R asynchronously clears the decade counter and sets the carry output and Y 0 high. With CE low, the count is advanced on a low-to-high transition at C input. Alternatively, if C is high, the count is advanced on a high-to-low transition at CE. Each decoded output remains high for one full clock cycle. The carry output is high while Q0, Q 1, Q2, Q3 or Q4 is high, then is low while Q5, Q6, Q7, Q8 or Q9 is high.