HD74HCT137 - 3-to-8-line Decoder/Demultiplexer with Address Latch

Product Overview

Hitachi Semiconductor

Part number	HD74HCT137
Manufacturer	Hitachi Semiconductor
File Size	56.20 KB
Description	3-to-8-line Decoder/Demultiplexer with Address Latch
Datasheet	HD74HCT137 Datasheet
Additional preview pages of the HD74HCT137 datasheet.

The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs.

When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches.

As long as GL remains high no address changes will be recognized.

LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (A, B, C to Y) = 18 ns typ (C L = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HCT137 Function Table Inputs Enable GL X X L L L L L L L L H G1 X L H H H H H H H H H G2 H X L L L L L L L L.

HD74HCT1G00 - 2-input NAND Gate (Renesas Technology)
HD74HCT1G08 - 2-input AND Gate (Renesas Technology)
HD74HCT1G32 - High Speed CMOS two input OR gate Using Silicon Gate CMOS Process (Renesas Technology)
HD74HCT1G66 - Analog Switch (Renesas Technology)
HD74HCT238 - 3-to-8-line Decoder/Demultiplexer (Renesas)
HD74HC00 - Quad. 2-input NAND Gates (Renesas)
HD74HC01 - Quad. 2-input NAND Gates (Renesas)
HD74HC02 - Quad. 2-input NOR Gates (Renesas)
HD74HC04 - Hex Inverters (Renesas)
HD74HC05 - Hex Inverters (Renesas)

Other Datasheets by Hitachi Semiconductor

Published: Mar 23, 2005 |