HD74HCT137 Description
The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized.
HD74HCT137 Key Features
- LSTTL Output Logic Level patibility as well as CMOS Output patibility High Speed Operation: tpd (A, B, C to Y) = 18 ns t
- 4.4 4.13
- Input current Quiescent supply current Iin I CC
- GL to Y G1 to Y G2 to Y A, B or C to Y
- 16 20 10
- 20 25 13
- 0.05 0°