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HD74HCT137 Datasheet 3-to-8-line Decoder/demultiplexer With Address Latch

Manufacturer: Hitachi Semiconductor (now Renesas)

Overview: HD74HCT137 3-to-8-line Decoder/Demultiplexer with Address Latch.

General Description

The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs.

When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches.

As long as GL remains high no address changes will be recognized.

Key Features

  • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (A, B, C to Y) = 18 ns typ (C L = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HCT137 Function Table Inputs Enable GL X X L L L L L L L L H G1 X L H H H H H H H H H G2 H X L L L L L L L L.

More Datasheets from Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HCT138 3-to-8-line Decoder/Demultiplexer
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HD74HCT126 Quad. Bus Buffer Gates (with 3-state outputs)
HD74HCT1G04 High speed CMOS inverter using silicon gate CMOS process
HD74HCT00A Quad. 2-input Positive NAND Gates
HD74HCT04A Hex Inverters
HD74HCT08A Quad. 2-input Positive AND Gates
HD74HCT237 3-to-8-line Decoder/Demultiplexer with Address Latch
HD74HCT238 3-to-8-line Decoder/Demultiplexer
HD74HCT240 Octal Buffers/Line Drivers/Line Receivers(with inverted 3-state outputs)

HD74HCT137 Distributor