HD74LS112
Description
19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) + 0...
- Part: HD74LS112
- Description: Dual J-K Negative-edge-triggered Flip-Flops
- Manufacturer: Hitachi Semiconductor
- Size: 76.76 KB
Datasheets by Manufacturer
| Part Number | Manufacturer | Description |
|---|---|---|
| HD74LS112P | Renesas | Dual J-K Negative-edge-triggered Flip-Flops |
| HD74LS112 | Renesas | Dual J-K Negative-edge-triggered Flip-Flops |
| HD74LS11 | Renesas | Triple 3-input Positive AND Gates |