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HD74LV174A - Hex D-type Flip-Flops with Clear

General Description

This device contains 6 master-slave flip-flops with a common clock and common clear.

Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input.

The clear input when low, sets all outputs to a low state.

Key Features

  • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max. ) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max. ) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) Function Table Inputs CLR L H H H Note: H: L: X: ↑: ↓: CLK X ↑ ↑ ↓ High level Low level Immaterial Low to high transiti.

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Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HD74LV174A Hex D-type Flip-Flops with Clear ADE-205-269 (Z) 1st Edition April 1999 Description This device contains 6 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state. Low-voltage and high-speed operation is suitable for battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • • • • • • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.