Datasheet Details
| Part number | HD74SSTV16857 |
|---|---|
| Manufacturer | Hitachi Semiconductor (now Renesas) |
| File Size | 154.31 KB |
| Description | 1:1 14-bit SSTL-2 Registered Buffer |
| Datasheet |
 HD74SSTV16857 Datasheet
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General Description
The HD74SSTV16857 is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.
Data flow from D to Q is controlled by differential clock pins (CLK, CLK) and the RESET.
Key Features
- Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.
- Differential SSTL_2 (Stub series terminated logic) CLK signal.
- Flow through architecture optimizes PCB layout.
- Package type Package type TSSOP-48 pin TVSOP-48 pin Package code TTP-48DB TTP-48DEV Package suffix T N Taping code EL (1,000 pcs / Reel) EL (1,000 pcs / Reel) HD74SSTV16857 Function Table Inputs RESET L H H H H: L: X: ↑: ↓: Note: CLK X ↓ ↓ L or H CLK X ↑ ↑ H or L D X H L X L.
