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HM514400C - 1/048/576-word X 4-bit Dynamic Random Access Memory

General Description

Pin name A0 to A9 A0 to A9 I/O1 to I/O4 RAS CAS WE OE VCC VSS Function Address input Refresh address input Data-in/Data-out Row address strobe Column address strobe Read/Write enable Output enable Power (+5 V) Ground 4 Block Diagram RAS Row Driver Row Driver RAS Control Circuit 256 k Memory Ar

Key Features

  • Single 5 V (±10%).
  • High speed.
  • Access time 60 ns/70 ns/80 ns (max).
  • Low power dissipation.
  • Active mode 605 mW/550 mW/495 mW (max).
  • Standby mode 11 mW (max) 0.55 mW (max) (L-version).
  • Fast page mode capability.
  • 1024 refresh cycles : 16 ms 1024 refresh cycles : 128 ms (L-version).
  • 3 variations of refresh.
  • RAS-only refresh.
  • CAS-before-RAS refresh.
  • Hidden refresh HM514400B/BL, HM514400C/CL S.

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Full PDF Text Transcription for HM514400C (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for HM514400C. For precise diagrams, tables, and layout, please refer to the original PDF.

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ADE-203-269A (Z) 1,048,576-word × 4-bit Dynamic Random Access Memory Rev. 1.0 Nov. 29, 1994 The Hitachi HM514400B/BL, HM514400C/CL are CMOS dynamic RAM organized 1,048,576word × 4-bit. HM514400B/BL, HM514400C/CL have realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM514400B/BL, HM514400C/CL offer Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM514400B/BL, HM514400C/CL to be packaged in standard 300-mil 26-pin plastic SOJ, standard 400-mil 20-pin plastic ZIP and 26pin plastic TSOP II.