HM514400CL - 1/048/576-word X 4-bit Dynamic Random Access Memory
Hitachi Semiconductor (now Renesas)
General Description
Pin name A0 to A9 A0 to A9 I/O1 to I/O4 RAS CAS WE OE VCC VSS Function Address input Refresh address input Data-in/Data-out Row address strobe Column address strobe Read/Write enable Output enable Power (+5 V) Ground
4
Block Diagram
RAS
Row Driver
Row Driver
RAS Control Circuit
256 k Memory Ar
Full PDF Text Transcription for HM514400CL (Reference)
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HM514400CL. For precise diagrams, and layout, please refer to the original PDF.
ADE-203-269A (Z) 1,048,576-word × 4-bit Dynamic Random Access Memory Rev. 1.0 Nov. 29, 1994 The Hitachi HM514400B/BL, HM514400C/CL are CMOS dynamic RAM organized 1,048,57...
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chi HM514400B/BL, HM514400C/CL are CMOS dynamic RAM organized 1,048,576word × 4-bit. HM514400B/BL, HM514400C/CL have realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM514400B/BL, HM514400C/CL offer Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM514400B/BL, HM514400C/CL to be packaged in standard 300-mil 26-pin plastic SOJ, standard 400-mil 20-pin plastic ZIP and 26pin plastic TSOP II.
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