HM62W16255H Datasheet | Hitachi Semiconductor

HM62W16255H Series 4M High Speed SRAM (256-kword × 16-bit) ADE-203-751D (Z) Rev. 1.0 Sep. 15, 1998 Description The HM62W16255H is a 4-Mbit high speed static RAM organized 256-kword × 16-bit. It has realized high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell)and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. The HM62W16255H is packaged in 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII for high density surface mounting. Features - Single 3.3 V supply: 3.3 V ± 0.3V - Access time: 12/15 ns (max) - pletely static memory  No clock or timing strobe required - Equal access and cycle times - Directly TTL patible  All inputs and outputs - Operating current: 180/160 m A (max) - TTL standby current: 60/50 m A (max) - CMOS standby current: 5 m A (max) : 1m A (max) (L-version) - Data retension current: 0.6 m A (max) (L-version) - Data retension voltage: 2.0 V (min) (L-version) - Center VCC and VSS type pinout HM62W16255H Series Ordering Information Type No. HM62W16255HJP-12 HM62W16255HJP-15 HM62W16255HLJP-12 HM62W16255HLJP-15 HM62W16255HTT-12 HM62W16255HTT-15 HM62W16255HLTT-12 HM62W16255HLTT-15 Access time 12 ns 15 ns 12 ns 15 ns 12 ns 15 ns 12 ns 15 ns 400-mil 44-pin plastic SOJ (TTP-44DE) Package 400-mil 44-pin plastic SOJ (CP-44D) Pin Arrangement HM62W16255HJP/HLJP Series A0 A1 A2 A3 A4 CS I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE UB LB I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A14 A13 A12 A11 A10 HM62W16255HTT/HLTT Series A0 A1 A2 A3 A4 CS I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36...