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HM658128A - 131072-word x 8-bit High Speed CMOS Pseudo Static RAM

General Description

Symbol A0 to A16 I/O0 to I/O7 RFSH CE OE WE CS VCC VSS Pin name Address inputs Data input/output Refresh Chip enable Output enable Write enable Chip select Power supply Ground 3 HM658128A Series Block Diagram A0 Address latch control Row decoder Memory matrix (512 × 256) × 8 A8 I/O 0 www.DataS

Key Features

  • Single 5 V (± 10%).
  • High speed.
  • Access time CE Access time: 80/100/120 ns.
  • Cycle time Random read/ Write cycle time: 130/160/190 ns.
  • Low power:.
  • Active: 300 mW (typ).
  • Standby: 350 µW (typ) (LL-version) 500 µW (typ) (L-version).
  • All inputs and outputs TTL compatible.
  • Non multiplexed address.
  • 512 refresh cycles (8 ms).
  • Refresh functions.
  • Address refresh.
  • Automatic refresh.

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Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HM65256B 32768 word x 8 Bit High Speed Psuedo Statie RAM
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ADE-203-188H(Z) HM658128A Series 131072-word × 8-bit High Speed CMOS Pseudo Static RAM Rev. 8.0 Jun. 5, 1995 The Hitachi HM658128A is a pseudo-static RAM organized as 131,072-word × 8-bit. HM658128A realizes low power consumption and high speed www.DataSheet4U.com access time by employing 1.3 µm CMOS process technology. The HM658128A supports 3 refresh functions: address refresh, auto refresh and self refresh. Low power version dissipates only 350 µW (typ)/500 µW (typ) in self refresh mode and retains the data with battery. The HM658128A is pin-compatible with 1-Mbit static RAM. Ordering Information Type No.