HD74AC158 Datasheet | Hitachi Semiconductor

Description The HD74AC158 is a high-speed quad 2-input multiplexer. It selects four bits of data from two source using the mon Select and Enable inputs. The four buffered outputs present the selected data in the inverted form. The HD74AC158 can also be used as a function generator. Feature - Outputs Source/Sink 24 m A Pin Arrangement S 1 I0a 2 I1a 3 Za 4 I0b 5 I1b 6 Zb 7 GND 8 (Top view) 16 VCC 15 E 14 I0c 13 I1c 12 Zc 11 I0d 10 I1d 9 Zd Logic Symbol I0a I1a I0b I1b I0c I1c Iod I1d S Za Zb Zc Zd Pin Names I0a to I0d I1a to I1d E S Za to Zd Source 0 Data Inputs Source 1 Data Inputs Enable Input Select Input Outputs Functional Description The HD74AC158 quad 2-input multiplexer selects four bits of data from two sources under the control of a mon Select input (S) and presents the data in inverted form at the four outputs. The Enable Input (E) is active-LOW. When E is HIGH, all of the outputs ( Z) are forced HIGH regardless of all other inputs. The HD74AC158 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. A mon use of the HD74AC158 is the moving of data from two groups of registers to four mon output busses. The particular register from which the data es is determined by the state of the Select input. A less obvious use is as a function generator. The HD74AC158 can generate four functions of two variables with one variable mon. This is useful for implementing gating functions. Truth Table Inputs E H L L L L H : L : X : S X L L H H High Voltage Level Low Voltage Level Immaterial I0 X L H X X I1 X X X L H Output Z H H L H L Logic Diagram I0a I1a I0b I1b I0c I1c I0d I1d E S Za Zb Zc Zd Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. DC Characteristics (unless otherwise specified) Item Maximum quiescent supply current...