HD74ALVCH162835 Datasheet | Hitachi Semiconductor

Description Data flow from A to Y is controlled by the output enable (OE ). The device operates in the transparent mode when LE is high. The A data is latched if CLK is held at a high or low logic level. If LE is low, the A bus data is stored in the latch flip flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 m A, include 26 Ω resistors to reduce overshoot and undershoot. Features - VCC = 2.3 V to 3.6 V - Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) - Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) - High output current ±12 m A (@V CC = 3.0 V) - Bus hold on data inputs eliminates the need for external pullup / pulldown resistors - All outputs have equivalent 26 Ω series resistors, so no external resistors are required. Function Table Inputs OE H L L L L L L LE X H H L L L L CLK X X X ↑ ↑ H L A X L H L H X X Z L H L H Y0 Y0 - 1 - 2 Output Y H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Notes: 1. Output level before the indicated steady state input conditions were established, provided that CLK is high before LE goes low. 2. Output level before the indicated steady state input conditions were established. Pin Arrangement NC 1 NC 2 Y1 3 GND 4 Y2 5 Y3 6 VCC 7 Y4 8 Y5 9 Y6 10 GND 11 Y7 12 Y8 13 Y9 14 Y10 15 Y11 16 Y12 17 GND 18 Y13 19 Y14 20 Y15 21 VCC 22 Y16 23 Y17 24 GND 25 Y18 26 OE 27 LE 28 56 GND 55 NC 54 A1 53 GND 52 A2 51 A3 50 VCC 49 A4 48 A5 47 A6 46 GND 45 A7 44 A8 43 A9 42 A10 41 A11 40 A12 39 GND 38 A13 37 A14 36 A15 35 VCC 34 A16 33 A17 32 GND 31 A18 30 CLK 29 GND (Top view) Absolute Maximum Ratings Item Supply voltage Input voltage - 1 - 1, 2 Symbol VCC VI VO I IK I OK IO I CC or IGND PT Tstg Ratings - 0.5 to 4.6 - 0.5 to 4.6 - 0.5...