HD74HC78 Datasheet | Hitachi Semiconductor

Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each flip-flop has independent J, K, and preset inputs and Q and Q outputs. Two flip-flops are controlled by a mon clear and a mon clock. Preset and clear are independent of the clock and acplished by a low logic level on the corresponding input. Features - - - - - High Speed Operation: tpd (Clock to Q) = 20 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) Function Table Inputs Preset L H L H H H H H H H Note: Clear H L L H H H H H H H L H Clock X X X J X X X L L H H X X X K X X X L H L H X X X Outputs Q H L H- Q L H H- 1 No change L H Toggle No change No change No change H L 1. Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset and Clear go HIGH simultaneously. Pin Arrangement CK 1 1PR 2 1J 3 VCC 4 CLR 5 2PR 6 2K 7 (Top view) K CK J CLR PR Q Q K CK J CLR PR Q Q 14 1K 13 1Q 12 1Q 11 GND 10 2J 9 2Q 8 2Q Block Diagram (1//2) To Other FF PR CLR J K # CK CK # CK # CK CK CK CK CK # CK CK # CK To Other FF DC Characteristics Ta = 25°C Item Input voltage Symbol VIH Ta = - 40 to +85°C Max - - - 0.5 1.35 1.8 - - - - - 0.1 0.1 0.1 0.33 0.33 ±1.0 20 µA µA I OL = 4 m A I OL = 5.2 m A Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA V I OH = - 4 m A I OH = - 5.2 m A Vin = VIH or VIL I OL = 20 µA V Vin = VIH or VIL I OH = - 20 µA V Unit V Test Conditions VCC (V) Min Typ Max Min 2.0 4.5 6.0 1.5 - 3.15 - 4.2 - - - - - - - - - - 0.5 1.5 3.15 4.2 -...