HD74HC83 Datasheet | Hitachi Semiconductor

Description This improved full adder performs the addition of two 4-bit binary numbers. The sum ( ) output are provided for each bit and the resultant carry (C4) is obtained from the fourth bit. This adder features full internal look ahead across all four bit generating the carry term in ten nanoseconds typically. This provides the system designer with partial look-ahead performance at the economy and reduced package count of a ripple-carry implementation. Features - - - - - High Speed Operation: tpd (Ai or Bi to Zi ) = 16 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Outputs Inputs A1/A3 L H L H L H L H L H L H L H L H H : L : X : Note: B1/B3 L L H H L L H H L L H H L L H H A2/A4 L L L L H H H H L L L L H H H H B2/B4 L L L L L L L L H H H H H H H H When C0 = L/When C2 = L ∑1/∑3 L H H L L H H L L H H L L H H L ∑2/∑4 L L L H H H H L H H H L L L L H C2/C4 L L L L L L L H L L L H H H H H When C0 = H/When C2 = H ∑1/∑3 H L L H H L L H H L L H H L L H ∑2/∑4 L H H H H L L L H L L L L H H H C2/C4 L L L L L H H H L H H H H H H H High level Low level Irrelevant Input conditions at A 1, B1, A2, B2 and C 0 are used to determine outputs ∑1 and ∑2 and the value of the internal carry C2. The value at C 2, A3, B3, A4 and B4 are than used to determine outputs ∑3, ∑4 and C 4 Pin Arrangement A4 1 Σ3 2 A3 3 B3 4 VCC 5 Σ2 6 B2 7 A2 8 (Top view) Σ2 B2 A2 B1 A1 Σ1 A4 Σ3 A3 B3 B4 Σ4 C4 C0 16 B4 15 Σ4 14 C4 13 C0 12 GND 11 B1 10 A1 9 Σ1 Block Diagram (1//2) C4 B4 A4 Σ4 B3 A3 Σ3 B2 A2 Σ2 B1 A1 C0 Σ1 DC Characteristics Ta = 25°C Item Input voltage Symbol VIH Ta = - 40 to +85°C Max - - - 0.5 1.35 1.8 - - - - - 0.1 0.1 0.1 0.33 0.33 ±1.0 40 µA µA I OL = 4 m A I OL = 5.2 m A Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA V I OH = - 4 m A I OH = - 5.2 m A Vin = VIH or VIL I OL =...