HD74HC85 Datasheet | Hitachi Semiconductor

Description The HD74HC85 id designed for high speed parison of two four bit words. This circuit has eight parison input, 4 for each word; three cascade inputs (A < B, A > B, A = B); and three decision outputs (A < B, A > B, A = B). The result of a parison is indicated by a high level on one of the decision outputs. thus it may be determined whether one word is “greater than,” “less than,” or “equal to” the other word. by connecting the outputs of the least significant stage to the cascade inputs of the enxt stage, words of greater than four bits can be pared. In addition the least significant stage must have a high level applied to the A = B input, and a low level to the A < B, and A > B inputs. Features - - - - - High Speed Operation: tpd (Data Word Input to Output) = 20 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Data Word Inputs A3, B3 A2, B2 A1, B1 X X X X A1 > B1 A1 < B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A0, B0 X X X X X X A0 > B0 A0 < B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 A0 = B0 Cascading Inputs A > Bin X X X X X X X X L L H H X A = Bin X X X X X X X X L L L L H A < Bin X X X X X X X X L H L H X Outputs A > Bout A = Bout A < Bout H L H L H L H L H L H L L L L L L L L L L L L L L H L H L H L H L H H H L L L A3 > B3 X A3 < B3 X A3 = B3 A2 > B2 A3 = B3 A2 < B2 A3 = B3 A2 = B2 A3 = B3 A2 = B2 A3 = B3 A2 = B2 A3 = B3 A2 = B2 A3 = B3 A2 = B2 A3 = B3 A2 = B2 A3 = B3 A2 = B2 A3 = B3 A2 = B2 A3 = B3 A2 = B2 Pin Arrangement B3 Data 1 Input A<B 2 A=B 3 A>B 4 A>B 5 A=B 6 A<B 7 GND 8 (Top view) A<B B3 A3 16 VCC 15 A3 14 B2 13 A2 12 A1 11 B1 10 A0 9 B0 A=B In B2 A>B A>B A2 A1 A=B out B1 A<B B0 A0 Logic Diagram B3 A3 A>Bout B2 A2 B1 A1 A<Bout B0 A0 A<Bin A=Bin A>Bin A=Bout DC Characteristics Ta = 25°C Item Input voltage Symbol VIH Ta = - 40 to...