HD74HCT620 Datasheet | Hitachi Semiconductor

Description This octal transceiver is designed for asynchronous two-way munication between data buses. The control function implementation allows for maximum flexibility in timng. This device allows data transmission from A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the enable inputs (GBA and GAB). The enable inputs can be used to disable the device so that the buses are affectively isolated. The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of GBA and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16 in all) will remain at their last states. The 8-bit codes appearing on the two sets of buses will be identical for the HD74HCT623 or plementary for the HD74HCT620. Features - - - - - - LSTTL Output Logic Level patibility as well as CMOS Output patibility High Speed Operation: tpd (Bus to Bus) = 15 ns typ (CL = 50 p F) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HCT620/HD74HCT623 Function Table Enable Input GBA L H H L GAB L H L H Operation HD74HCT620 B data to A bus A data to B bus Isolation B data to A bus, A data to B bus HD74HCT623 B data to A bus A data to B bus Isolation B data to A bus, A data to B bus Pin Arrangement Enable GAB A1 A2 A3 A4 A5 A6 A7 A8 1 2 3 4 5 6 7 8 9 20 VCC 19 Enable GBA 18 B1 17 B2 16 B3 15 B4 14 B5 13 B6 12 B7 11 B8 (Top view) GND 10 HD74HCT620/HD74HCT623 Block Diagram GAB GBA VCC A1 VCC B1 A2 A3 A4 A5 A6 A7 A8 B2 B3 B4 B5 B6 B7 B8 HD74HCT620/HD74HCT623 HD74HCT623 GAB GBA VCC A1 VCC B1 A2 A3 A4 A5 A6 A7 A8 B2 B3 B4 B5 B6 B7 B8 Absolute Maximum Ratings Item Supply voltage range Input voltage Output voltage DC...