HD74LV174A Datasheet | Hitachi Semiconductor

Description This device contains 6 master-slave flip-flops with a mon clock and mon clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state. Low-voltage and high-speed operation is suitable for battery-powered products (e.g., notebook puters), and the low-power consumption extends the battery life. Features - - - - - - VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 m A (@VCC = 3.0 V to 3.6 V), ±12 m A (@VCC = 4.5 V to 5.5 V) Function Table Inputs CLR L H H H Note: H: L: X: ↑: ↓: CLK X ↑ ↑ ↓ High level Low level Immaterial Low to high transition High to low transition D X H L X Output Q L H L no change Pin Arrangement CLR 1 1Q 2 1D 3 2D 4 2Q 5 3D 6 3Q 7 GND 8 16 VCC 15 6Q 14 6D 13 5D 12 5Q 11 4D 10 4Q 9 CLK (Top view) Absolute Maximum Ratings Item Supply voltage range Input voltage range- 1 1, 2 Symbol VCC VI VO Ratings - 0.5 to 7.0 - 0.5 to 7.0 - 0.5 to VCC + 0.5 - 0.5 to 7.0 Unit V V V Conditions Output voltage range- Output: H or L VCC: OFF Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at Ta = 25°C (in still air)- 3 I IK I OK IO I CC or IGND PT - 20 ±50 ±25 ±50 785 500 m A m A m A m A m W VI < 0 VO < 0 or VO > VCC VO = 0 to VCC SOP TSSOP Storage temperature Tstg - 65 to 150 °C Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum....