HD74LV595A Datasheet | Hitachi Semiconductor

Description This device each contains an 8-bit serial-in, parallel-out shift registers that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift register anf the storage register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading. Both the shift register anf the storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register state will always be one clock pulse ahead of the storage register. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook puters), and the low-power consumption extends the battery life. Features - - - - - - VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 m A (@VCC = 3.0 V to 3.6 V), ±12 m A (@VCC = 4.5 V to 5.5 V) Function Table Inputs SER X X X L H X X X Note: H: L: X: ↑: ↓: SRCLK X X X ↑ ↑ ↓ X X SRCLR X X L H H H X X RCLK X X X X X X ↑ ↓ G H L X X X X X X Function Force outputs into high-impedance state Enable paralle output Reset shift register Shift data into shift register Shift data into shift register Shift register remains unchanged Transfer shift register contents to latch register Latch register remains unchanged High level Low level Immaterial Low to high transition High to low transition Pin Arrangement QB 1 QC 2 QD 3 QE 4 QF 5 QG 6 QH 7 GND 8 16 VCC 15 QA 14 SER 13 G 12 RCLK 11 SRCLK 10 SRCLR 9 QH' (Top view) Absolute Maximum Ratings Item Supply voltage range Input voltage range- 1 1, 2 Symbol VCC VI VO Ratings - 0.5 to 7.0 - 0.5 to 7.0 - 0.5 to VCC + 0.5 - 0.5 to 7.0 Unit V V V Conditions Output voltage range- Output: H or L Output: Z or...