HD74SSTV16857 Datasheet | Hitachi Semiconductor

Description The HD74SSTV16857 is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input. Data flow from D to Q is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to maintain noise margins. When RESET is low, all registers are reset and all outputs are low. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. Features - Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input - Differential SSTL_2 (Stub series terminated logic) CLK signal - Flow through architecture optimizes PCB layout - Package type Package type TSSOP-48 pin TVSOP-48 pin Package code TTP-48DB TTP-48DEV Package suffix T N Taping code EL (1,000 pcs / Reel) EL (1,000 pcs / Reel) Function Table Inputs RESET L H H H H: L: X: ↑: ↓: Note: CLK X ↓ ↓ L or H CLK X ↑ ↑ H or L D X H L X L H L Q0 - 1 Output Q High level Low level Immaterial Low to high transition High to low transition 1. Output level before the indicated steady state input conditions were established. Rev.6, Jun. 2001, page 2 of 15 Pin Arrangement Q1 1 Q2 2 GND 3 V DDQ 4 Q3 5 Q4 6 Q5 7 GND 8 V DDQ 9 Q6 10 Q7 11 V DDQ 12 GND 13 Q8 14 Q9 15 V DDQ 16 GND 17 Q10 18 Q11 19 Q12 20 V DDQ 21 GND 22 Q13 23 Q14 24 48 D1 47 D2 46 GND 45 V CC 44 D3 43 D4 42 D5 41 D6 40 D7 39 CLK 38 CLK 37 V CC 36 GND 35 V REF 34 RESET 33 D8 32 D9 31 D10 30 D11 29 D12 28 V CC 27 GND 26 D13 25 D14 (Top view) Rev.6, Jun. 2001, page 3 of 15 Absolute Maximum Ratings Item Supply voltage Input voltage - 1 - 1, 2 Symbol VCC or VDDQ VI VO IIK IOK IO ICC, IDDQ or IGND PT Tstg Ratings - 0.5 to 3.6 - 0.5 to VDDQ+0.5 - 0.5 to VDDQ+0.5 ±50 ±50 ±50 ±100 115 - 65 to +150 Unit V V V m A m A m A m A °C / W °C Conditions Output...