H5MS2562JFR-J3M Overview
and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied.
H5MS2562JFR-J3M Key Features
- Mobile DDR SDRAM
- MODE RERISTER SET, EXTENDED MODE REGISTER SET and STATUS REGISTER READ
- Keep to the JEDEC Standard regulation (Low Power DDR SDRAM)
- Mobile DDR SDRAM INTERFACE
- x16 bus width
- Multiplexed Address (Row address and Column address)
- CAS LATENCY
- Programmable CAS latency 2 or 3 supported
- SUPPLY VOLTAGE
- 1.8V device: VDD and VDDQ = 1.7V to 1.95V